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IR3081A
DATA SHEET XPHASETM VR 10 CONTROL IC
DESCRIPTION
The IR3081A Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible way to implement a complete VR 10 power solution. The "Control" IC provides overall system control and interfaces with any number of "Phase ICs" which each drive and monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. The IR3081A is intended for VRD 10 or VRM/EVRD 10 applications that use external VCCVID/VTT circuits. The IR3081A is functionally equivalent to the IR3081, but incorporates the following modifications: * Under Voltage Lockout start threshold increased from 9.1V to 9.7V (typical) and hysteresis increased from 200mV to 800mV (typical). * Hysteresis (52mV typical) added to the SS/DEL comparator to prevent Power Good output chatter. * Over current discharge current increased from 6uA to 40uA (typical) to reduce the over current delay time. * IIN pin precondition circuit added to disable current sharing in the phase ICs during soft start.
FEATURES
* * * * * * * * * * * * * * 6 bit VR 10 compatible VID with 0.5% overall system accuracy 1 to X phases operation with matching phase ICs Programmable Dynamic VID Slew Rate No Discharge of output capacitors during Dynamic VID step-down (can be disabled) +/-300mV Differential Remote Sense Programmable 150kHz to 1MHz oscillator Programmable VID Offset and Load Line output impedance Programmable Softstart Programmable Hiccup Over-Current Protection with Delay to prevent false triggering Simplified Powergood provides indication of proper operation and avoids false triggering Operates from 12V input with 9.1V Under-Voltage Lockout 6.8V/5mA Bias Regulator provides System Reference Voltage Enable Input Small thermally enhanced 28L MLPQ package
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IR3081A
APPLICATION CIRCUIT
12V
RVCC 10 ohm CVCC 0.1uF
25
27
23
28
26
24
22
POWERGOOD ENABLE
CSS/DEL
ENABLE
SS/DEL
RMPOUT
PWRGD
N/C
LGND
VCC
RMPOUT VBIAS
VBIAS BBFB 21 20 19 18 17 16 15 RDRP1 CDRP RDRP RCP CCP 0.1uF
1
OSCDS VID5 VID0 VID1 VID2 VID3
VID5 VID0 VID1 VID2 VID3 VID4
2 3 4 5 6 7
IR3081A CONTROL IC
VOSNSROSC TRM1 TRM2 TRM3 TRM4
EAOUT FB VDRP IIN OCSET VDAC
EA
5 Wire Analog Bus to Phase ICs
CCP1
VID4
ISHARE
ROCSET CFB
VDAC
8
9
10
11
12
13
ROSC
14
RVDAC
RFB1
RFB
CVDAC
VOSENSE+ VOSENSE-
Remote Sense
ORDERING INFORMATION
Device IR3081AMTR IR3081AM
Order Quantity 3000 per reel 100 piece strips
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IR3081A
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature.................150oC Storage Temperature Range......................-65oC to 150oC ESD Rating.............................................HBM Class 1C JEDEC standard
PIN # 1 2-7 8, 9, 11,12 10 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PIN NAME OSCDS VID0-5 TRM1-4 VOSNSROSC VDAC OCSET IIN VDRP FB EAOUT BBFB VBIAS VCC LGND RMPOUT SS/DEL PWRGD N/C ENABLE
VMAX 20V 20V Do Not Connect 0.5V 20V 20V 20V 20V 20V 20V 10V 20V 20V 20V n/a 20V 20V 20V n/a 20V
VMIN -0.3V -0.3V Do Not Connect -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V n/a -0.3V
ISOURCE 1mA 10mA Do Not Connect 10mA 1mA 1mA 1mA 1mA 5mA 1mA 10mA 1mA 1mA 1mA 50mA 1mA 1mA 1mA n/a 1mA
ISINK 1mA 10mA Do Not Connect 10mA 1mA 1mA 1mA 1mA 5mA 1mA 20mA 1mA 1mA 50mA 1mA 1mA 1mA 20mA n/a 1mA
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IR3081A
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 9.5V VCC 14V, 0 oC TJ 100 oC PARAMETER VDAC Reference System Set-Point Accuracy TEST CONDITION -0.3V VOSNS- 0.3V, Connect FB to EAOUT, Measure V(EAOUT) - V(VOSNS-) deviation from Table 1. Applies to all VID codes. RROSC = 41.9k RROSC = 41.9k 0V VID0-5 VCC MIN TYP 0.5 MAX UNIT %
Source Current Sink Current VID Input Threshold VID Input Bias Current Regulation Detect Comparator Input Offset Regulation Detect to EAOUT Delay BBFB to FB Bias Current Ratio VID 11111x Blanking Delay VID Step Down Detect Blanking Time VID Down BB Clamp Voltage VID Down BB Clamp Current Error Amplifier Input Offset Voltage
68 47 500 -5 -5
80 55 600 0 0 130
92 63 700 5 5 200 1.05
A A mV A mV ns A/A ns s
0.95 Measure Time till PWRGD drives low Measure from VID inputs to EAOUT Percent of VDAC voltage 70 3.5 -3
1.00 800 1.7 75 6.2 4
80 12 8
% mA mV
FB Bias Current DC Gain Gain-Bandwidth Product Source Current Sink Current Max Voltage Min Voltage IIN Precondition Reset Comparator Threshold VDRP Buffer Amplifier Input Offset Voltage Bandwidth (-3dB) Slew Rate IIN Bias Current IIN Precondition Set Comparator Threshold Offset IIN Precondition Pull Down Resistance
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Connect FB to EAOUT, and measure V(EAOUT) - V(DAC). Applies to all VID codes from table 1 and -0.3V VOSNS 0.3V. Note 2 RROSC = 41.9k Note 1 Note 1
VBIAS-VEAOUT (referenced to VBIAS) Normal operation or Fault mode
-31 90 4 0.4 0.7 125 30 450
-29.5 100 7 0.6 1.2 250 100 600
-28 105 0.8 1.7 375 150 750
A dB MHz mA mA mV mV mV
V(VDRP) - V(IIN), 0.8V V(IIN) 5.5V Note 1 Note 1 Difference of preconditioning active voltage and SS/DEL-FB offset voltage SS/DEL=0V.
-13 1 -2.0 350 7.5
-2 6 10 -0.75 600 15
6
mV MHz V/s A mV K
0 850 22.5
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IR3081A
PARAMETER Oscillator Switching Frequency Peak Voltage (5V typical, measured as % of VBIAS) Valley Voltage (1V typical, measured as % of VBIAS) VBIAS Regulator Output Voltage Current Limit Soft Start and Delay SS/DEL to FB Input Offset Voltage Charge Current Discharge Current Charge/Discharge Current Ratio Charge Voltage Over Current Discharge Current Over Current Delay Time Delay Comparator Threshold Delay Comparator Threshold Delay Comparator Hysteresis Over-Current Comparator Input Offset Voltage OCSET Bias Current PWRGD Output Output Voltage Leakage Current Enable Input Threshold voltage Bias Current VCC Under-Voltage Lockout Start Threshold Stop Threshold Hysteresis General VCC Supply Current VOSNS- Current TEST CONDITION RROSC = 41.9k RROSC = 41.9k RROSC = 41.9k MIN 255 70 11 TYP 300 71 14 MAX 345 74 16 UNIT kHz % %
-5mA I(VBIAS) 0
6.5 -30 0.85 40 4 10 3.5
6.8 -15 1.3 70 6 11.5 3.8 40 250 65 115 52 0 -29.5 150 0
7.1 -6 1.5 100 9 13 4.0
V mA V A A A/A V uA us mV mV mV mV A mV A mV A V V mV mA mA
With FB = 0V, adjust V(SS/DEL) until EAOUT drives high
CSS/DEL=0.1uF. Note 1 Relative to Charge Voltage, SS/DEL rising Relative to Charge Voltage, SS/DEL falling
150 35 85 32
350 95 145 72 10 -28 400 10 700 5 10.2 9.4 1200 14 -3.5
1V V(OCSET) 5V RROSC = 41.9k I(PWRGD) = 4mA V(PWRGD) = 5.5V
-10 -31
0V V(ENABLE) VCC
500 -5 9.2 8.4 600 8 -5.5
600 0 9.7 8.9 800 11 -4.5
Start - Stop
-0.3V VOSNS- 0.3V, All VID Codes
Note 1: Guaranteed by design, but not tested in production Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offset errors
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IR3081A
PIN DESCRIPTION
PIN# 1 2-7 8, 9, 11,12 10 13 14
PIN SYMBOL OSCDS VID0-5 TRM1-4 VOSNSROSC VDAC
15
OCSET
16
IIN
17 18
VDRP FB
19 20
EAOUT BBFB
21 22 23 24 25
VBIAS VCC LGND RMPOUT SS/DEL
26 27 28
PWRGD N/C ENABLE
PIN DESCRIPTION Apply a voltage greater than VBIAS to disable the oscillator. Used during factory testing & trimming. Ground or leave open for normal operation. Inputs to VID D to A Converter Used for precision post-package trimming of the VDAC voltage. Do not make any connection to these pins. Remote Sense Input. Connect to ground at the Load. Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET, BBFB, and VDAC bias currents Regulated voltage programmed by the VID inputs. Current Sensing and PWM operation are referenced to this pin. Connect an external RC network to VOSNS- to program Dynamic VID slew rate. Programs the hiccup over-current threshold through an external resistor tied to VDAC and an internal current source. Over-current protection can be disabled by connecting this pin to a DC voltage no greater than 6.5V (do not float this pin as improper operation will occur). Current Sense input from the Phase IC(s). To ensure proper operation bias to at least 250mV (don't float this pin). The pin is clamped to ground during the early stage of soft start to disable current sharing function in the phase ICs. Buffered IIN signal. Connect an external RC network to FB to program converter output impedance Inverting input to the Error Amplifier. Converter output voltage is offset from the VDAC voltage through an external resistor connected to the converter output voltage at the load and an internal current source. Output of the Error Amplifier Input to the Regulation Detect Comparator. Connect to converter output voltage and VDRP pin through resistor network to program recovery from VID step-down. Connect to ground to disable Body BrakingTM during transition to a lower VID code. 6.8V/5mA Regulated output used as a system reference voltage for internal circuitry and the Phase ICs. Power for internal circuitry Local Ground and IC substrate connection Oscillator Output voltage. Used by Phase ICs to program Phase Delay Controls Converter Softstart, Power Good, and Over-Current Delay Timing. Connect an external capacitor to LGND to program the timing. An optional resistor can be added in series with the capacitor to reduce the over-current delay time. Open Collector output that drives low during Softstart and any external fault condition. Connect external pull-up. No internal connection Enable Input. A logic low applied to this pin puts the IC into Fault mode.
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IR3081A
SYSTEM THEORY OF OPERATION
XPhaseTM Architecture The XPhaseTM architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can control converters of any phase number where flexibility facilitates the design trade-off of multiphase converters. The scalable architecture can be applied to other applications which require high current or multiple output voltages. As shown in Figure 1, the XPhaseTM architecture consists of a Control IC and a scalable array of phase converters each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e. bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator and latch, over-voltage protection, and current sensing and sharing. There is no unused or redundant silicon with the XPhaseTM architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.
POWER GOOD PHASE FAULT VR HOT 12V
GATE VOLTAGE REGULATOR
ENABLE
VID5 VID0 VID1 VID2 VID3 VID4
IR3081A CONTROL IC
PHASE FAULT >> BIAS VOLTAGE >> PHASE TIMING << CURRENT SENSE >> PWM CONTROL >> VID VOLTAGE BIAS VOLTAGE PHASE TIMING CURRENT SHARE PWM CONTROL VID VOLTAGE PHASE HOT CCS RCS CIN VOUT SENSE+
IR3086A PHASE IC
VOUT+ 0.1uF COUT VOUT-
VOUT SENSE-
PHASE FAULT BIAS VOLTAGE PHASE TIMING CURRENT SHARE PWM CONTROL VID VOLTAGE PHASE HOT CCS RCS
IR3086A PHASE IC
0.1uF
OC OC OC OC OC OC OC CONTROL BUS
ADDITIONAL PHASES
OC OC OC INPUT/OUTPUT
Figure 1. System Block Diagram
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IR3081A
PWM Control Method The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current.
VIN
CONTROL IC
BIASIN
50% DUTY CYCLE
SYSTEM REFERENCE VOLTAGE CLOCK PULSE GENERATOR
+
PHASE IC
PWM LATCH S PWM COMPARATOR
+ ENABLE + RESET DOMINANT
RAMP GENERATOR
VPEAK
RMPOUT
RPHS1
RAMPIN+
-
GATEH
VOSNS+ VOUT
COUT
VVALLEY
RAMPINEAIN
R
VBIAS
GATEL GND
+ VBIAS REGULATOR
RPHS2
VDAC VOSNS-
RPWMRMP
PWMRMP
+
VDAC
-
CPWMRMP
SCOMP
CSCOMP
RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER
BODY BRAKING COMPARATOR
+ -
EAOUT
ERROR AMP FB
RVFB
ISHARE 10K
+
20mV
RDRP
X34 DACIN
VDRP AMP
VDRP
IIN
BIASIN RAMPIN+ RAMPINEAIN
RPHS2 RPHS1 +
SYSTEM REFERENCE VOLTAGE CLOCK PULSE GENERATOR
PHASE IC
PWM LATCH S PWM COMPARATOR
+ ENABLE RESET DOMINANT
R
RPWMRMP
SCOMP
CPWMRMP CSCOMP
RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER
ISHARE 10K
+
20mV
X34 DACIN
Figure 2. PWM Block Diagram Frequency and Phase Timing Control The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 5V and 1V respectively. This signal is used to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RPHS1 and RPHS2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator waveform over the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for phase timing by swapping the RMPIN+ and RMPIN- pins, as shown in figure 2.
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+
-
-
+
PWMRMP
BODY BRAKING COMPARATOR
+ -
CURRENT SENSE AMPLIFIER
-
IFB
IROSC
+
-
-
VOSNS-
+
-
+ -
X 0.91
+ +
-
CURRENT SENSE AMPLIFIER
CSIN+
CCS RCS
CSIN-
GATEH
GATEL
X 0.91
CSIN+
CCS RCS
CSIN-
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IR3081A
50% RAMP DUTY CYCLE SLOPE = 80mV / % DC
RAMP (FROM CONTROL IC)
VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V)
SLOPE = 1.6mV / ns @ 200kHz SLOPE = 8.0mV / ns @ 1MHz
CLK1
CLK2
PHASE IC CLOCK PULSES
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
Figure 3. 8 Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the nonoverlap time. When the PWMRMP voltage exceeds the Error Amplifier's output voltage, the PWM latch is reset. This turns off the high side driver and then turns on the low side driver after the non-overlap time; it activates the Ramp Discharge Clamp, which quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide "single cycle transient response" where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 4 depicts PWM operating waveforms under various conditions.
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IR3081A
PHASE IC CLOCK PULSE
EAIN PWMRMP VDAC 91% VDAC
GATEH
GATEL
STEADY-STATE OPERATION
DUTY CYCLE INCREASE DUE TO LOAD INCREASE
DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, OCP, VID=11111X)
STEADY-STATE OPERATION
Figure 4. PWM Operating Waveforms Body BrakingTM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is;
TSLEW = L * ( I MAX - I MIN ) VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier's body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now;
TSLEW = L * ( I MAX - I MIN ) VO + VBODYDIODE
Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as "body braking" and is accomplished through the "0% Duty Cycle Comparator" located in the Phase IC. If the Error Amplifier's output voltage drops below 91% of the VDAC voltage this comparator turns off the low side gate driver. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 5. The equation of the sensing network is,
vC ( s ) = v L ( s ) R L + sL 1 = iL ( s ) 1 + sR CS C CS 1 + sR CS C CS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current.
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IR3081A
vL iL L RCS
Current Sense Amp
RL CCS
c v CS
VO CO
CSOUT Figure 5. Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 5. Its gain decreases with increasing temperature and is nominally 34 at 25C and 29 at 125C (-1470 ppm/C). This reduction of gain tends to compensate the 3850 ppm/C increase in inductor DCR. Since in most designs the Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and other Phases through an on-chip 10K resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the Control IC for voltage positioning and current limit protection. Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC. The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop.
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IR3081A
IR3081A THEORY OF OPERATION
Block Diagram The Block diagram of the IR3081A is shown in Fig. 6, and specific features are discussed in the following sections.
VCC UVLO COMPARATOR
VCC
+ 9.7V
8.9V ENABLE
START STOP +
FAULT LATCH SQ 0.2V DISCHARGE OVER COMPARATOR CURRENT
SET DOMINANT
PWRGD
-
+
+
+ 0.6V VCHG 3.8V
65mV 115mV
+
-
+ -
ON IDISCHG IDISCHG 6uA ICHGICHG 70uA SS/DEL VID5 VID0 VID1 VID2 VID3 VID4 BBFB VOSNSVBIAS IROSC IROSC IROSC IROSC VID CONTROL IROSC IROSC IROSC IROSC
+ 0.6V
+
-
VID STEP-DOWN VID DAC OUTPUT IROSC 1.2V VDAC FB IROSC IFB
VBIAS
50% DUTY CYCLE
RAMP GENERATOR
5.0V
IROSC CURRENT SOURCE GENERATOR
RMPOUT
ROSC
Figure 6. IR3081A Block Diagram VID Control A 6-bit VID voltage compatible with VR 10, as shown in Table 1, is available at the VDAC pin. A detailed block diagram of the VID control circuitry can be found in Figure 7. The VID pins require an external bias voltage and should not be floated. The VID input comparators, with 0.6V reference, monitor the VID pins and control the 6 bit Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer amplifier is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the Error Amplifier to provide a 0.5% system set-point accuracy. The actual VDAC voltage does not determine the system accuracy and has a wider tolerance.
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-
1.0V
+
+
VBIAS REGULATOR
+ 6.8V ROSC BUFFER AMPLIFIER
+
VID = 11111X
+ +
-
+
OFF
SS/DEL DISCHARGE
PRECONDITION RESET COMPARATOR
-
RESET DOMINANT
R
SOFT START CLAMP 1.3V
ERROR AMPLIFIER EAOUT DISABLE
-
-
OCICHG
SQ
10k
+
+
-
+ -
ENABLE COMPARATOR
R DELAY COMPARATOR
+
IROSC OVER CURRENT COMPARATOR
+ SET THRESHOLD 0.7V (1.3-0.6V) PRECONDITION PRECONDITION SET COMPARATOR LATCH
IOCSET OCSET IIN VDRP AMPLIFIER VDRP
IDISCHG 40uA
-
+
-
+
LGND
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IR3081A
The IR3081A can accept changes in the VID code while operating and vary the DAC voltage accordingly. The sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the oscillator frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. It is desirable to prevent negative inductor currents in response to a request for a lower VID code. Negative current transforms the buck converter into a boost converter and transfers energy from the output capacitors back into the input voltage. This energy can cause voltage spikes and damage the silver box or other components unless they are specifically designed to handle it. Furthermore, power is wasted during the transfer of energy from the output back to the input. The IR3081A includes circuitry that turns off both control and synchronous MOSFETs in response to a lower VID code so that the load current instead of the inductor discharges the output capacitors. A lower VID code is detected by the VID step-down detect comparator which monitors the "fast" output of the DAC (plus 7mV for noise immunity) compared to the "slow" output of the VDAC pin. If a dynamic VID step down is detected, the body brake latch is set and the output of the error amplifier is pulled down to 75% of the DAC voltage by the VID body brake clamp. This triggers the Body BrakingTM function, which turns off both high side and low side drivers in the phase ICs. The converter's output voltage needs to be monitored and compared to the VDAC voltage to determine when to resume normal operation. Unfortunately, the voltage on the FB pin can be pulled down by its compensation network during the sudden decrease in the Error Amplifier's output voltage so an additional pin BBFB is provided. The BBFB pin is connected to the converter output voltage and VDRP pin with resistors of the same value as on the FB pin and therefore provides an un-corrupted representation of converter output voltage. The regulation detect comparator compares the BBFB to the VDAC voltage and resets the body brake latch releasing the error amplifier's output and allowing normal operation to resume. Body BrakingTM during a transition to a lower VID code can be disabled by connecting the BBFB pin to ground.
800ns BLANKING
VID = 11111X DETECT
VID5 VID0 VID1 VID2 VID3 VID4 VID INPUT COMPARATORS (1 OF 6 SHOWN)
DIGITAL TO ANALOG CONVERTER
VDAC BUFFER AMP "FAST" VDAC
+ -
+
ISOURCE
"SLOW" VDAC
VDAC
0.6V
VOSNSEAOUT VID DOWN BB CLAMP TO ERROR AMP
ENABLE
+
7mV
75%
S
RESET DOMINANT
1.7us BLANKING
VID STEP-DOWN DETECT COMPARATOR
R REGULATION DETECT COMPARATOR
Figure 7. VID Control Block Diagram
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+
BODY BRAKE LATCH
-
-
+
-
+
+ -
ISINK
-
+
IBBFB BBFB IROSC (From Current Source Generator)
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IR3081A
Processor Pins (0 = low, 1 = high)
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vout (V) 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 OFF4 OFF4 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000
Processor Pins (0 = low, 1 = high)
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Vout (V) 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000
Note: 3. Output disabled (Fault mode) Table 1. Voltage Identification (VID) Adaptive Voltage Positioning Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in Figure 8. Resistor RFB is connected between the Error Amplifier's inverting input pin FB and the converter's output voltage. An internal current source whose value is programmed by the same external resistor that programs the oscillator frequency pumps current into the FB pin. The error amplifier forces the converter's output voltage lower to maintain a balance at its inputs. RFB is selected to program the desired amount of fixed offset voltage below the DAC voltage. The voltage at the VDRP pin is a buffered version of the share bus and represents the sum of the DAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RDRP. Since the Error Amplifier will force the loop to maintain FB to be equal to the VDAC reference voltage, an additional current will flow into the FB pin equal to (VDRP-VDAC) / RDRP. When the load current increases, the adaptive positioning voltage increases accordingly. More current flows through the feedback resistor RFB, and makes the output voltage lower proportional to the load current. The positioning voltage can be programmed by the resistor RDRP so that the droop impedance produces the desired converter output impedance. The offset and slope of the converter output impedance are referenced to and therefore independent of the VDAC voltage.
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IR3081A
Control IC
VDAC
Phase IC
Current Sense Amplifier
10k -
EAOUT
Vo
ISHARE
VDAC
FB
IFB RFB
RDRP
VDRP Amplifier
+
VDRP
Phase IC
Current Sense Amplifier CSIN+ CSIN-
... ...
IIN
ISHARE VDAC
10k
Figure 8. Adaptive voltage positioning Inductor DCR Temperature Correction If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional correction. The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as shown in Figure 9. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. A similar network must be placed on the BBFB to ensure proper operation during a transition to a lower VID code with Body BrakingTM.
Control IC
VDAC
Error Amplifier
+
EAOUT
FB
RFB RFB2
Rt
Vo
IFB
AVP Amplifier
+
RDRP
VDRP
IIN
Figure 9. Temperature compensation of inductor DCR Remote Voltage Sensing To reduce the effect of impedance in the ground plane, the VOSNS- pin is used for remote sensing and connected directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to a separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed transients are fed directly into the error amplifier without delay.
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+
-
+
Error Amplifier
+
CSIN+
CSIN-
-
-
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IR3081A
Soft Start, Over-Current Fault Delay, and Hiccup Mode The IR3081A has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay and hiccup mode timing. A charge current of 70uA and discharge current of 6uA control the up slope and down slope of the voltage at the SS/DEL pin respectively Figure 10 depicts the various operating modes as controlled by the SS/DEL function. If there is no fault, the SS/DEL pin will begin to be charged. The error amplifier output is clamped low until SS/DEL reaches 1.3V. The error amplifier will then regulate the converter's output voltage to match the SS/DEL voltage less the 1.3V offset until it reaches the level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.71V and allows the PWRGD signal to be asserted. SS/DEL finally settles at 3.8V, indicating the end of the soft start. Under Voltage Lock Out and VID=11111x faults as well as a low signal on the ENABLE input immediately sets the fault latch causing SS/DEL to begin to discharge. The SS/DEL capacitor will continue to discharge down to 0.2V. If the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur. A delay is included if an over-current condition occurs after a successful soft start sequence. This is required since over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an overcurrent fault occurs during normal operation it will initiate the discharge of the capacitor at SS/DEL but will not set the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge below the 90mV offset of the delay comparator, the Fault latch will be set pulling the error amplifier's output low inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The SS/DEL capacitor will continue to discharge until it reaches 0.2V and the fault latch is reset allowing a normal soft start to occur. If an over-current condition is again encountered during the soft start cycle the fault latch will be set without any delay and hiccup mode will begin. During hiccup mode the charge to discharge current ratio results in a fixed 7.9% hiccup mode duty cycle regardless of at what point the over-current condition occurs. However, the hiccup frequency is determined by the load current and over-current set value. The over-current delay can be reduced by adding a resistor in series with the SS/DEL capacitor. The delay comparator's offset voltage is reduced by the drop in the resistor caused by the discharge current. The value of the series resistor should be 10K or less to avoid interference with the soft start function. If SS/DEL pin is pulled below 0.9V, the converter can be disabled. Under Voltage Lockout (UVLO) The UVLO function monitors the IR3081A's VCC supply pin and ensures that IR3081A has a high enough voltage to power the internal circuit. The IR3081A's UVLO is set higher than the minimum operating voltage of compatible Phase ICs thus providing UVLO protection for them as well. During power-up the fault latch is reset when VCC exceeds 9.7V and there is no other fault. If the VCC voltage drops below 8.9V the fault latch will be set. For converters using a separate 5V supply for gate driver bias an external UVLO circuit can be added to prevent any operation until adequate voltage is present. A diode connected between the 5V supply and the SS/DEL pin provides a simple 5V UVLO function. Over Current Protection (OCP) The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin voltage, which is proportional to the average current plus DAC voltage, exceeds the OCSET voltage, the over-current protection is triggered. VID = 11111X Fault VID codes of 111111 and 111110 will set the fault latch and disable the error amplifier. An 800ns delay is provided to prevent a fault condition from occurring during Dynamic VID changes. Enable Input Pulling the ENABLE pin below 0.6V sets the Fault Latch.
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IR3081A
VCC (12V) 8.9V UVLO
ENABLE
SS/DEL
3.735V 3.685V 1.3V
VOUT
PWRGD
OCP THRESHOLD IOUT START-UP (ENABLE GATES FAULT MODE) NORMAL OPERATION (VOUT CHANGES DUE TO LOAD OCP AND VID CHANGES) DELAY HICCUP OVER-CURRENT PROTECTION RE-START AFTER OCP POWER-DOWN (VCC GATES FAULT MODE)
Figure 10. Operating Waveforms Power Good Output The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.71V. The PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage regulation within the design limits can logically be assured however, assuming no component failure in the system. Load Current Indicator Output The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can be retrieved by a differential amplifier which subtracts the VDAC voltage from the VDRP voltage. System Reference Voltage (VBIAS) The IR3081 supplies a 6.8V/5mA precision reference voltage from the VBIAS pin. The oscillator ramp amplitude tracks the VBIAS voltage, which should be used to program the Phase IC trip points to minimize phase delay errors. Precondition of IIN during Soft Start IIN pin is clamped during the early stage of soft start, which disables current sharing function in the phase ICs to prevent PWM ramp from pulling too low. When V(SS/DEL)<0.7V, the precondition latch is set, and IIN is clamped to ground through a 10k resistor. After V(SS/DEL) is 1.3V above V(FB), error amplifier output is released. When V(EAOUT) jumps above 0.6V, the precondition latch is reset and the IIN clamp is removed. Normal current sharing in the phase ICs then resumes.
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IR3081A
APPLICATION INFORMATION
POWERGOOD VRHOT PHASE FAULT
12V
RVCC 10 ohm QGATE VGATE
RCSCCS+ CCSRBIASIN CVCC 0.1uF RPHASE11 RGATE 20k DBST 20 19 18 17 16 RCS+
DGATE
BIASIN DACIN PHSFLT CSIN+ CSIN-
CBST 15 14 13 12 11 L
CIN
1 2 3 4 5 CSS/DEL 0.1uF
VOUT SENSE+
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
VCCH
IR3086A PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
VOUT+
DISTRIBUTION IMPEDANCE COUT
ENABLE
28 26 27
RPHASE12
CFB RBBFB
VOUTCVCCL RVCC RPWMRMP 10
25
24
23
22
6
7
CPWMRMP 8
9
RFB1
RFB
VOUT SENSE-
ENABLE
PWRGD
SS/DEL
N/C
LGND
RMPOUT
VCC
1
OSCDS VID5 VID0 VID1 VID2 VID3
VBIAS BBFB
21 20 19 18 17 16 15 RDRP1 CDRP CCP1 RCP CCP RBBDRP
RPHASE13
VID5 VID0 VID1 VID2 VID3 VID4
2 3 4 5 6 7
CSCOMP
CVCC
IR3081A CONTROL IC
VOSNSROSC TRM1 TRM2 TRM3 TRM4
EAOUT FB VDRP IIN OCSET VDAC
RCSCCS+ CCSRBIASIN RPHASE21 20k 20 19 18 17 16 RCS+ DBST
VID4
RDRP
BIASIN
DACIN
PHSFLT
CSIN+
CSIN-
8
9
10
11
12
13
14
CBST 15 14 L 13 12 11
CIN
ROCSET
1 2
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
VCCH
ROSC RVDAC RSHARE
3 4 5 CVDAC RPHASE22
IR3086A PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
CVCCL RVCC RPWMRMP
6
7
8
9
RPHASE23
CSCOMP
CPWMRMP
10
CVCC
RCSCCS+ CCSRBIASIN RPHASE31 20k 20 19 18 17 16 RCS+ DBST
PHSFLT
BIASIN
DACIN
CSIN+
CSIN-
CBST CIN VCCH 15 14 13 12 11 L
1 2 3 4 5 RPHASE32
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
IR3086A PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
CVCCL RVCC RPWMRMP
6
7
CPWMRMP 8
9
RPHASE33
CSCOMP
10
CVCC
RCSCCS+ RBIASIN RPHASE41 20k 19 18 20 17 16 CCSRCS+ DBST
BIASIN
DACIN
PHSFLT
CSIN+
CSIN-
CBST CIN VCCH 15 14 13 12 11 L
1 2 3 4 5 RPHASE42
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
IR3086A PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
CVCCL RVCC RPWMRMP
6
7
CPWMRMP 8
9
RPHASE43
CSCOMP
10
CVCC
RCSCCS+ RBIASIN RPHASE51 20k 20 19 18 17 16 CCSRCS+ RCS+ CBST CIN VCCH 15 14 13 12 11 L DBST
BIASIN
DACIN
1 2 3 4 5 RPHASE52
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
IR3086A PHASE IC
PWMRMP LGND VCC
PHSFLT
CSIN+ GATEH PGND GATEL VCCL
CSIN-
CVCCL RVCC RPWMRMP
6
7
CPWMRMP 8
9
RPHASE53
CSCOMP
10
CVCC
RCSCCS+ RBIASIN RPHASE61 20k 20 19 18 17 16 CCSRCS+ RCS+ CBST 15 14 13 12 11 L DBST
BIASIN
DACIN
PHSFLT
CSIN+
CSIN-
CIN
1 2 3 4 5 RPHASE62
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
VCCH
IR3086A PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
CVCCL RVCC RPWMRMP
6
7
CPWMRMP 8
9
RPHASE63
CSCOMP
10
CVCC
Figure 11. IR3081A/IR3086A Six-Phase VRM/EVRD 10 Converter
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IR3081A
DESIGN PROCEDURES - IR3081A AND IR3086A CHIPSET
IR3081A EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3081A generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which is set by the external resistor ROSC according to the curve in Figure 13. Soft Start Capacitor CSS/DEL Because the capacitor CSS/DEL programs four different time parameters, i.e. soft start delay time, soft start time, over-current latch delay time, and power good delay time, they should be considered together while choosing CSS/DEL. The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10. After the ENABLE pin voltage rises above 0.6V, there is a soft-start delay time tSSDEL, after which the error amplifier output is released to allow the soft start. The soft start time tSS represents the time during which converter voltage rises from zero to VO. tSS can be programmed by an external capacitor, which is determined by Equation (1).
C SS / DEL = I CHG * t SS 70 * 10 -6 * t SS = VO VO
(1)
Once CSS/DEL is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the delay time tVccPG from output voltage (VO) in regulation to Power Good are fixed and shown in Equations (2), (3) and (4) respectively.
tSSDEL = tOCDEL = CSS / DEL *1.3 CSS / DEL *1.3 = I CHG 70 *10-6 CSS / DEL * 0.115 CSS / DEL * 0.115 = I OCDISCHG 40 *10- 6
(2)
(3)
tVccPG =
CSS / DEL * (3.8 - 0.065 - VO - 1.3) CSS / DEL * (3.735 - VO - 1.3) = I CHG 70 *10- 6
(4)
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in Equation (5), where ISINK is the sink current of VDAC pin as shown in Figure 15. The resistor RVDAC is used to compensate VDAC circuit and is determined by Equation (6). The slew rate of VDAC up-slope SRUP is proportional to that of VDAC down-slope and is given by Equation (7), where ISOURCE is the source current of VDAC pin as shown in Figure15.
CVDAC = I SINK SR DOWN
(5)
RVDAC = 0.5 + SRUP =
Page 19 of 39
3.2 10 -15 CVDAC 2
(6)
I SOURCE CVDAC
(7)
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IR3081A
Over Current Setting Resistor ROCSET The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant temperature coefficient of 3850 ppm/C, and therefore the maximum inductor DCR can be calculated from Equation (8), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature T_ROOM respectively.
R L _ MAX = R L _ ROOM [1 + 3850 * 10 -6 (T L _ MAX - TROOM )]
(8)
The current sense amplifier gain of IR3086A decreases with temperature at the rate of 1470 ppm/C, which compensates part of the inductor DCR increase. The phase IC die temperature is only a couple of degrees Celsius higher than the PCB temperature due to the low thermal impedance of MLPQ package. The minimum current sense amplifier gain at the maximum phase IC temperature TIC_MAX is calculated from Equation (9).
GCS _ MIN = GCS _ ROOM [1 - 1470 * 10 -6 (TIC _ MAX - TROOM )]
(9)
The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset (VCS_OFST) of the amplifier itself and that created by the amplifier input bias currents flowing through the current sense resistors RCS+ and RCS-.
VCS _ TOFST = VCS _ OFST + I CSIN + RCS + - I CSIN - RCS -
(10)
The over current limit is set by the external resistor ROCSET as defined in Equation (11), where ILIMIT is the required over current limit. IOCSET, the bias current of OCSET pin, changes with switching frequency setting resistor ROSC and is determined by the curve in Figure 14. KP is the ratio of inductor peak current over average current in each phase and is calculated from Equation (12).
ROCSET = [
KP =
I LIMIT RL _ MAX (1 + K P ) + VCS _ TOFST ] GCS _ MIN / I OCSET n
(11)
(VI - VO ) VO /( L VI f SW 2) IO / n
(12)
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP A resistor between FB pin and the converter output is used to create output voltage offset VO_NLOFST, which is the difference between VDAC voltage and output voltage at no load condition. Adaptive voltage positioning further lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. RFB is not only determined by IFB, the current flowing out of FB pin as shown in Figure 14, but also affected by the adaptive voltage positioning resistor RDRP and total input offset voltage of current sense amplifiers. RFB and RDRP are determined by (13) and (14) respectively.
R FB = R L _ MAX VO _ NLOFST - VCS _ TOFST n RO I FB R L _ MAX
(13)
R DRP =
R FB R L _ MAX GCS _ MIN n RO
(14)
Body BrakingTM Related Resistors RBBFB and RBBDRP The body brakingTM during Dynamic VID can be disabled by connecting BBFB pin to ground. If the feature is enabled, Resistors RBBFB and RBBDRP are needed to restore the feedback voltage of the error amplifier after Dynamic VID step down. Usually RBBFB and RBBDRP are chosen to match RFB and RDRP respectively.
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IR3081A
IR3086A EXTERNAL COMPONENTS PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP PWM ramp is generated by connecting the resistor RPWMRMP between a voltage source and PWMRMP pin as well as the capacitor CPWMRMP between PWMRMP and LGND. Choose the desired PWM ramp magnitude VRAMP and the capacitor CPWMRMP in the range of 100pF and 470pF, and then calculate the resistor RPWMRMP from Equation (15). To achieve feed-forward voltage mode control, the resistor RRAMP should be connected to the input of the converter. VO (15) RPWMRMP = VIN * f SW * CPWMRMP * [ln(VIN - VDAC ) - ln(VIN - VDAC - VPWMRMP )] Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSThe DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS+ and capacitor CCS+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS+ represents the inductor current. If the two time constants are not the same, the AC component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS+ and calculate RCS+ as follows. L RL (16) RCS + = C CS + The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across RCS+, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage positioning is adopted. To reduce the offset voltage, a resistor RCS- should be added between the amplifier inverting input and the converter output. The resistor RCS- is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input.
RCS - = I CSIN + RCS + I CSIN -
(17)
If RCS- is not used, RCS+ should be chosen so that the offset voltage is small enough. Usually RCS+ should be less than 2 k and therefore a larger CCS+ value is needed. Over Temperature Setting Resistors RHOTSET1 and RHOTSET2 The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (C) of phase IC. Determine the relationship between the die temperature of phase IC and the temperature of the power converter according to the power loss, PCB layout and airflow etc, and then calculate HOTSET threshold voltage corresponding to the allowed maximum temperature from Equation (18).
V HOTSET = 4.73 * 10 -3 * T J + 1.241
(18)
There are two ways to set the over temperature threshold, central setting and local setting. In the central setting, only one resistor divider is used, and the setting voltage is connected to HOTSET pins of all the phase ICs. To reduce the influence of noise on the accuracy of over temperature setting, a 0.1uF capacitor should be placed next to HOTSET pin of each phase IC. In the local setting, a resistor divider per phase is needed, and the setting voltage is connected to HOTSET pin of each phase. The 0.1uF decoupling capacitor is not necessary. Use VBIAS as the reference voltage. If RHOTSET1 is pre-selected, RHOTSET2 can be calculated as follows. V R (19) RHOTSET 2 = HOTSET 1 HOTSET VBIAS - VHOTSET
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IR3081A
Phase Delay Timing Resistors RPHASE1 and RPHASE2 The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at RMPIN+ or RMPIN- depending on which slope of the oscillator ramp is used for the phase delay programming of phase IC, as shown in Figure 3. If the upslope is used, RMPIN+ pin of the phase IC should be connected to RMPOUT pin of the control IC and RMPIN- pin should be connected to the resistor divider. When RMPOUT voltage is above the trip voltage at RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time. If down slope is used, RMPIN- pin of the phase IC should be connected to RMPOUT pin of the control IC and RMPIN+ pin should be connected to the resistor divider. When RMPOUT voltage is below the trip voltage at RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time. Use VBIAS voltage as the reference for the resistor divider since the oscillator ramp magnitude from control IC tracks VBIAS voltage. Try to avoid both edges of the oscillator ramp for better noise immunity. Determine the ratio of the programming resistors corresponding to the desired switching frequencies and phase numbers. If the resistor RPHASEx1 is pre-selected, the resistor RPHASEx2 is determined as:
R PHASEx 2 = RAPHASEx R PHASEx1 1 - RAPHASEx
(20)
Combined Over Temperature and Phase Delay Setting Resistors RPHASE1, RPHASE2 and RPHASE3 The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one resistor per phase. Calculate the HOTSET threshold voltage VHOTSET corresponding to the allowed maximum temperature from Equation (18). If the over temperature setting voltage is lower than the phase delay setting voltage, VBIAS*RAPHASEx, connect RMPIN+ or RMPIN- pin between RPHASEx1 and RPHASEx2, and connect HOTSET pin between RPHASEx2 and RPHASEx3. Pre-select RPHASEx1,
RPHASEx 2 = RPHASEx3 = ( RAPHASEx VBIAS - VHOTSET ) * RPHASEx1 VBIAS (1 - RAPHASEx ) VHOTSET RPHASEx1 VBIAS * (1 - RAPHASEx )
(21)
(22)
If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RAPHASEx, connect HOTSET pin between RPHASEx1 and RPHASEx2 and connect RMPIN+ or RMPIN- between RPHASEx2 and RPHASEx3 respectively. Pre-select RPHASEx1,
R PHASEx 2 = RPHASEx 3 = (V HOTSET - RAPHASEx V BIAS ) R PHASEx1 V BIAS - V HOTSET RAPHASEx VBIAS * RPHASEx1 VBIAS - VHOTSET
(23)
(24)
Bootstrap Capacitor CBST Depending on the duty cycle and gate drive current of the phase IC, a 0.1uF to 1uF capacitor is needed for the bootstrap circuit. Decoupling Capacitors for Phase IC 0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.
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IR3081A
VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage loop compensation much easier. Resistors RFB and RDRP are chosen according to Equations (13) and (14), and the selection of compensation types depends on the output capacitors used in the converter. For the applications using Electrolytic, Polymer or ALPolymer capacitors and running at lower frequency, type II compensation shown in Figure 12(a) is usually enough. While for the applications using only ceramic capacitors and running at higher frequency, type III compensation shown in Figure 12(b) is preferred. For applications where AVP is not required, the compensation is the same as for the regular voltage mode control. For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency, type III compensation is required as shown in Figure 12(b) with RDRP and CDRP removed.
CCP1
CCP1
VO+
RFB
RCP
CCP
RCP
CCP
RFB1
CFB
FB
-
VO+
RFB
FB
EAOUT
EAOUT
EAOUT EAOUT
VDRP
RDRP
VDAC
+
VDRP
RDRP
VDAC
+
CDRP
(a) Type II compensation
(b) Type III compensation
Figure 12. Voltage loop compensation network Type II Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, and determine RCP and CCP from Equations (25) and (26), where LE and CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. (2 fC ) 2 LE CE RFB VPWMRMP (25) RCP = VO * 1 + (2 * fC * C * RC ) 2
C CP = 10 L E C E RCP
(26)
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Type III Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by Equations (27) and (28), where RLE is the equivalent resistance of inductor DCR.
f C1 =
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RDRP 2 * CE GCS * RFB RLE
(27)
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C1 = 90 - A tan(0.5)
180
(28)
Choose the desired crossover frequency fc around fc1 estimated by Equation (27) or choose fc between 1/10 and 1/5 of the switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB /Dec around the crossover frequency. Choose resistor RFB1 according to Equation (29), and determine CFB and RDRP from Equations (30) and (31).
R FB1 = 1 R FB 2
to
R FB1 =
2 R FB 3
(29)
CFB =
1 4 fC RFB1
( R FB + R FB1 ) C FB R DRP
(30)
C DRP =
(31)
RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency and transient load response. Determine RCP and CCP from Equations (32) and (33).
RCP = (2 fC )2 LE CE RFB VPWMRMP VO
10 L E C E RCP
(32)
C CP =
(33)
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Type III Compensation for Non-AVP Applications Resistor RFB is chosen according to Equations (13), and resistor RDRP and capacitor CDRP are not needed. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase margin c. Calculate K factor from Equation (34), and determine the component values based on Equations (35) to (39),
K = tan[ ( C + 1.5)] 4 180
RCP = RFB CCP = CCP1 = CFB = R FB1 = ( 2 LE CE fC ) 2 VPWMRMP VO K
(34)
(35)
K 2 fC RCP 1 2 fC K RCP K 2 fC RFB 1 2 f C K C FB
(36)
(37)
(38)
(39)
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CURRENT SHARE LOOP COMPENSATION The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. A capacitor from SCOMP to ground is usually enough for the share loop compensation. Choose the crossover frequency of current share loop (fCI) based on the crossover frequency of voltage loop (fC), and determine the CSCOMP,
CSCOMP = 0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2 * fCI * CE * (VO I O )] * FMI VO 2 fCI *1.05 *106
(40)
Where FMI is the PWM gain in the current share loop,
FMI = RPWMRMP * CPWMRMP * f SW *V PWMRMP (VI - VPWMRMP - VDAC ) * (VI - VDAC )
(41)
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DESIGN EXAMPLE 1 - VRM 10 2U CONVERTER
SPECIFICATIONS Input Voltage: VI=12 V DAC Voltage: VDAC=1.35 V No Load Output Voltage Offset: VO_NLOFST=20 mV Output Current: IO=105 ADC Maximum Output Current: IOMAX=120 ADC Output Impedance: RO=0.91 m VCC Ready to VCC Power Good Delay: tVccPG=0-10mS Soft Start Time: tSS=2 mS Over Current Delay: tOCDEL<0.5mS Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS Over Temperature Threshold: TPCB=115 C POWER STAGE Phase Number: n=6 Switching Frequency: fSW=400 kHz Output Inductors: L=220 nH, RL=0.47 m Output Capacitors: AL-Polymer, C=560uF, RC= 7m, Number Cn=10 IR3081A EXTERNAL COMPONENTS Oscillator Resistor Rosc Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13. For switching frequency of 400kHz per phase, choose ROSC=30.1k Soft Start Capacitor CSS/DEL Determine the soft start capacitor from the required soft start time.
C SS / DEL = I CHG t SS 70 *10 -6 2 *10 -3 = = 0.1uF VO 1.35 - 20 *10 -3
The soft start delay time is
tSSDEL = CSS / DEL 1.3 0.1*10-6 1.3 = = 1.86mS I CHG 70 *10-6
The power good delay time is
tVccPG = CSS / DEL * (3.735 - VO - 1.3) 0.1*10-6 * (3.735 - 1.33 - 1.3) = = 1.58ms I CHG 70 *10- 6
Over current delay time is
tOCDEL = CSS / DEL * 0.115 0.1 *10-6 * 0.115 = = 0.29ms I OCDISCHG 40 *10- 6
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VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC From Figure 15, the sink current of VDAC pin corresponding to 400kHz (ROSC=30.1k) is 76uA. Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.
CVDAC = I SINK 76 * 10 -6 = = 30.4nF , Choose CVDAC=33nF SR DOWN 2.5 * 10 -3 / 10 -6
Calculate the programming resistor.
RVDAC = 0.5 + 3.2 * 10 -15 CVDAC 2 = 0.5 + 3.2 * 10 -15 (33 * 10 -9 ) 2 = 3.5
From Figure 15, the source current of VDAC pin is 110uA. The VDAC up-slope slew rate is
SRUP = I SOURCE 110 * 10 -6 = = 3.3mV / uS CVDAC 33 * 10 -9
Over Current Setting Resistor ROCSET The room temperature is 25C and the target PCB temperature is 100 C. The phase IC die temperature is about 1 C higher than that of phase IC, and the inductor temperature is close to PCB temperature. Calculate Inductor DC resistance at 100 C,
RL _ MAX = RL _ ROOM [1 + 3850*10-6 (TL _ MAX - TROOM )] = 0.47 *10-3 [1 + 3850*10-6 (100 - 25)] = 0.61m
The current sense amplifier gain is 34 at 25C, and its gain at 101C is calculated as,
G CS _ MIN = G CS _ ROOM [1 - 1470 *10 -6 (T IC _ MAX - T ROOM )] = 34 [1 - 1470 *10 -6 (101 - 25)] = 30.2
Set the over current limit at 135A. From Figure 14, the bias current of OCSET pin (IOCSET) is 41uA with ROSC=30.1k. The total current sense amplifier input offset voltage is 0.55mV, which includes the offset created by the current sense amplifier input resistor mismatch. Calculate constant KP, the ratio of inductor peak current over average current in each phase,
KP = (V I - VO ) VO /( L V I f SW 2) (12 - 1.33) 1.33 /( 220 *10 -9 12 400 * 10 3 2) = = 0.3 I LIMIT / n 135 / 6
ROCSET = [
I LIMIT RL _ MAX (1 + K P ) + VCS _ TOFST ] GCS _ MIN / I OCSET n
=(
135 0.61 *10 -3 1.3 + 0.55 *10 - 3 ) 30.2 /( 41 *10 - 6 ) = 13.3k 6
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP From Figure 14, the bias current of FB pin is 41uA with ROSC=30.1k.
R FB = R L _ MAX V O _ NLOFST - V CS _ TOFST n R O I FB R L _ MAX RFB RL _ MAX GCS _ MIN n RO = = 0 .61 * 10 -3 20 * 10 -3 - 0 .55 * 10 -3 6 0 .91 * 10 -3 41 * 10 - 6 0 .61 * 10 - 3 = 1.21k = 365
RDRP =
365 0.61 * 10-3 30.2 6 0.91 * 10- 3
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Body Braking Related Resistors RBBFB and RBBDRP N/A. The body braking during Dynamic VID is disabled. IR3086A EXTERNAL COMPONENTS PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP Set PWM ramp magnitude VPWMRMP=0.8V. Choose 220pF for PWM ramp capacitor CPWMRMP, and calculate the resistor RPWMRMP, VO RPWMRMP = VIN f SW CPWMRMP [ln(VIN - VDAC ) - ln(VIN - VDAC - VPWMRMP )]
= 1.33 12 400 *10 3 220 *10 -12 [ln(12 - 1.35) - ln(12 - 1.35 - 0.8)] = 16.1k , choose RPWMRMP=16.2k
Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSChoose CCS+=47nF, and calculate RCS+,
RCS + = L RL 220 *10-9 /(0.47 *10-3 ) = = 10.0k CCS + 47 *10-9
The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor RCS-,
RCS - = 0.25 0.25 RCS + = 10.0 *103 = 6.2k , choose RCS-=6.19k 0.4 0.4
Over Temperature Setting Resistors RHOTSET1 and RHOTSET2 Use central over-temperature setting and set the temperature threshold at 115 C, which corresponds to the IC die temperature of 116 C. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds.
V HOTSET = 4.73 * 10 -3 * TJ + 1.241 = 4.73 * 10 -3 116 + 1.241 = 1.79V
Pre-select RHOTSET1=10.0k,
R HOTSET 2 = R HOTSET 1 V HOTSET 10 *10 3 1.79 = = 3.57 k V BIAS - V HOTSET 6.8 - 1.79
Phase Delay Timing Resistors RPHASE1 and RPHASE2 Use central over-temperature setting and set the temperature threshold at 115 C, which corresponds to the IC die temperature of 116 C. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds. The phase delay resistor ratios for phases 1 to 6 at 400kHz of switching frequencies are RAPHASE1=0.628, RAPHASE2=0.415, RAPHASE3=0.202, RAPHASE4=0.246, RAPHASE5=0.441 and RAPHASE5=0.637 starting from downslope. Pre-select RPHASE11=RPHASE21=RPHASE31=RPHASE41=RPHASE51= RPHASE61=10k,
RPHASE12 = RAPHASE1 0.628 RPHASE11 = 10 *103 = 16.9k 1 - RAPHASE1 1 - 0.628
RPHASE22=7.15k, RPHASE32=2.55k, RPHASE42=3.24k, PPHASE52=7.87k, RPHASE62=17.4k
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Bootstrap Capacitor CBST Choose CBST=0.1uF Decoupling Capacitors for Phase IC and Power Stage Choose CVCC=0.1uF, CVCCL=0.1uF VOLTAGE LOOP COMPENSATION Type II compensation is used for the converter with AL-Polymer output capacitors. Choose the crossover frequency fc=40kHz, which is 1/10 of the switching frequency per phase, and determine Rcp and CCP.
RCP = (2 fC )2 LE CE RFB VRAMP VO * 1 + (2 * fC * C * RC )2 = (2 40 103 )2 (220 10-9 / 6) (560 10-6 10) 365 0.8 (1.35 - 20 10-3 ) * 1 + (2 * 40 *103 * 560 *10-6 * 7 *10-3 )2 = 2.0k
CCP =
10 LE CE RCP
=
10 (220 10-9 / 6) (560 10-6 *10) 2.0 103
= 71nF , Choose CCP=68nF
Choose CCP1=47pF to reduce high frequency noise. CURRENT SHARE LOOP COMPENSATION The crossover frequency of the current share loop fCI should be at least one decade lower than that of the voltage loop fC. Choose the crossover frequency of current share loop fCI=4kHz, and calculate CSCOMP,
FMI = RPWMRMP * CPWMRMP * f SW *V PWMRMP 16.2 *103 * 220 *10-12 * 400 *103 * 0.8 = = 0.011 (VI - VPWMRMP - VDAC ) * (VI - VDAC ) (12 - 0.8 - 1.35) * (12 - 1.35) 0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2 * fCI * CE * (VO I O )] * FMI VO 2 fCI *1.05 *106
CSCOMP =
=
0.65 *16.2 *10 3 *12 *105 * 34 * (0.47 *10 -3 6) * [1 + 2 * 4 *10 3 * 560 *10 -6 *10 * (1.33 - 105 * 9.1*10 -4 ) 105] * 0.011 (1.33 - 105 * 9.1*10 - 4 ) 2 4 *10 3 *1.05 *10 6
= 31.4nF
Choose CSCOMP=33nF.
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DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER
SPECIFICATIONS Input Voltage: VI=12 V DAC Voltage: VDAC=1.3 V No Load Output Voltage Offset: VO_NLOFST=20 mV Output Current: IO=105 ADC Maximum Output Current: IOMAX=120 ADC Output Impedance: RO=0.91 m VCC Ready to VCC Power Good Delay: tVccPG=0-10mS Soft Start Time: tSS=3mS Over Current Delay: tOCDEL<0.5mS Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS Over Temperature Threshold: TPCB=115 C POWER STAGE Phase Number: n=6 Switching Frequency: fSW=800 kHz Output Inductors: L=100 nH, RL=0.5 m Output Capacitors: Ceramic, C=22uF, RC= 2m, Number Cn=62 IR3081A EXTERNAL COMPONENTS Oscillator Resistor Rosc Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13 data sheet. For switching frequency of 800kHz per phase, choose ROSC=13.3k Soft Start Capacitor CSS/DEL Determine the soft start capacitor from the required soft start time.
CSS / DEL = I CHG tSS 70 *10-6 3 *10-3 = = 0.16uF , choose CSS/DEL=0.15uF VO 1.3 - 20 *10-3
The soft start delay time is
tSSDEL = CSS / DEL 1.3 0.15 *10-6 1.3 = = 2.8mS I CHG 70 *10- 6
The power good delay time is
tVccPG = CSS / DEL * (3.735 - VO - 1.3) 0.15 *10-6 * (3.735 - 1.33 - 1.3) = = 2.4ms I CHG 70 *10-6
Over current delay time is
tOCDEL = CSS / DEL * 0.115 0.15 *10-6 * 0.115 = = 0.43ms I OCDISCHG 40 *10- 6
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC From Figure 15, the sink current of VDAC pin corresponding to 800kHz (ROSC=13.3k) is 170uA. Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.
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CVDAC = I SINK 170 * 10 -6 = = 68nF SR DOWN 2.5 * 10 -3 / 10 -6
Calculate the programming resistor.
RVDAC = 0.5 + 3.2 * 10 -15 CVDAC
2
= 0.5 +
3.2 * 10 -15 (68 * 10 -9 ) 2
= 1.2
From Figure 15, the source current of VDAC pin is 250uA. The VDAC up-slope slew rate is
SRUP = I SOURCE 250 *10 -6 = = 3.7 mV / uS CVDAC 68 *10 -9
Over Current Setting Resistor ROCSET The room temperature is 25C and the target PCB temperature is 100 C. The phase IC die temperature is about 1 C higher than that of phase IC, and the inductor temperature is close to PCB temperature. Calculate Inductor DC resistance at 100 C,
RL _ MAX = RL _ ROOM [1 + 3850*10-6 (TL _ MAX - TROOM )] = 0.5 *10-3 [1 + 3850*10-6 (100 - 25)] = 0.64m
The current sense amplifier gain is 34 at 25C, and its gain at 101C is calculated as,
G CS _ MIN = G CS _ ROOM [1 - 1470 *10 -6 (T IC _ MAX - T ROOM )] = 34 [1 - 1470 *10 -6 (101 - 25)] = 30 .2
Set the over current limit at 135A. From Figure 14, the bias current of OCSET pin (IOCSET) is 90uA with ROSC=13.3k. The total current sense amplifier input offset voltage is 0.55mV, which includes the offset created by the current sense amplifier input resistor mismatch. Calculate constant KP, the ratio of inductor peak current over average current in each phase,
KP = (VI - VO ) VO /( L VI f SW 2) (12 - 1.28) 1.28 /(100 *10-9 12 800 *103 2) = = 0.32 135 / 6 I LIMIT / n RLIMIT RL _ MAX (1 + K P ) + VCS _ TOFST ] GCS _ MIN / I OCSET n
ROCSET = [ =(
135 0.64 *10 - 3 1.32 + 0.55 *10 -3 ) * 30.2 /(90 *10 - 6 ) = 6.34 k 6
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP From Figure 14, the bias current of FB pin is 90uA with ROSC=13.3k.
RFB = RL _ MAX VO _ NLOFST - VCS _ TOFST n RO I FB RL _ MAX RFB RL _ MAX GCS _ MIN n RO = = 0.64 *10-3 20 *10-3 - 0.55 *10-3 6 0.91 *10-3 = 162 90 *10-6 * 0.64 *10-3
RDRP =
162 0.64 *10-3 * 30.2 = 576 6 0.91 *10-3
Body Braking Related Resistors RBBFB and RBBDRP N/A. The body braking during Dynamic VID is disabled.
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IR3086A EXTERNAL COMPONENTS PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP Set PWM ramp magnitude VPWMRMP=0.75V. Choose 100pF for PWM ramp capacitor CPWMRMP, and calculate the resistor RPWMRMP, VO RPWMRMP = VIN * f SW * CPWMRMP * [ln(VIN - VDAC ) - ln(VIN - VDAC - VPWMRMP )]
= 1.28 12 800 *103 100 *10- 12 [ln(12 - 1.3) - ln(12 - 1.3 - 0.75)] = 18.2k
Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSChoose 47nF for capacitor CCS+, and calculate RCS+,
RCS + = L RL 100 *10-9 /(0.5 *10-3 ) = = 4.22k CCS + 47 *10-9
The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor RCS-,
RCS - = 0.25 0.25 RCS + = 4.22 *10 3 = 2.61k 0.4 0.4
Combined Over Temperature and Phase Delay Setting Resistors RPHASEx1, RPHASEx2 and RPHASEx3 The over temperature setting resistor divider is combined with the phase delay resistor divider. Set the temperature threshold at 115 C, which corresponds to the IC die temperature of 116 C, and calculate the HOTSET threshold voltage corresponding to the temperature thresholds.
V HOTSET = 4.73 * 10 -3 TJ + 1.241 = 4.73 * 10 -3 116 + 1.241 = 1.79V
The phase delay resistor ratios for phases 1 to 6 at 800kHz of switching frequencies are RAPHASE1=0.665, RAPHASE2=0.432, RAPHASE3=0.198, RAPHASE4=0.206, RAPHASE5=0.401 and RAPHASE5=0.597 starting from downslope. The over temperature setting voltage of phases 1, 2, 5, and 6 is lower than the phase delay setting voltage, VBIAS*RAPHASEx. Pre-select RPHASE11=10k,
RPHASEx 2 = RPHASEx3 = ( RAPHASEx VBIAS - VHOTSET ) * RPHASEx1 (0.665 6.8 - 1.79) 10 *103 = 12.1k = 6.8 (1 - 0.665) VBIAS (1 - RAPHASEx ) 1.79 12.1 *103 VHOTSET RPHASEx1 = 7.87 k = VBIAS * (1 - RAPHASEx ) 6.8 * (1 - 0.665)
RPHASE21=10k, RPHASE22=2.94k, RPHASE23=4.64k RPHASE51=10k, RPHASE52=2.32k, RPHASE53=4.42k RPHASE61=10k, RPHASE62=8.25k, RPHASE63=6.49k The over temperature setting voltage of Phases 3 and 4 is higher than the phase delay setting voltage, VBIAS*RAPHASEx. Pre-select RPHASEX1=10k,
R PHASE 32 = RPHASE 33 = (V HOTSET - RAPHASE 3 V BIAS ) R PHASE 31 (1.79 - 0.198 6.8) 10 *10 3 = 887 = V BIAS - V HOTSET 6.8 - 1.79 RAPHASE 3 VBIAS * RPHASE 31 0.198 6.8 10 *103 = 2.67 k = 6.8 - 1.79 VBIAS - VHOTSET
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RPHASE41=10k, RPHASE42=768, RPHASE43=2.80k Bootstrap Capacitor CBST Choose CBST=0.1uF Decoupling Capacitors for Phase IC and Power Stage Choose CVCC=0.1uF, CVCCL=0.1uF VOLTAGE LOOP COMPENSATION Type III compensation is used for the converter with only ceramic output capacitors. The crossover frequency and phase margin of the voltage loop can be estimated as follows.
f C1 = R DRP 576 = = 146 kHz -6 2 C E G CS R FB R LE 2 (62 22 * 10 ) 34 162 (0.5 * 10 - 3 / 6)
180
C1 = 90 - A tan(0.5)
Choose RFB1 =
= 63
2 2 RFB = 162 = 110 3 3
Choose the desired crossover frequency fc (=140kHz) around fc1 estimated above, and calculate
CFB = 1 4 fC RFB1 = 1 = 5.2nF , choose CFB=5.6nF 4 140 *103 110
CDRP =
( RFB + RFB1 ) CFB (162 + 110) 5.6 *10-9 = = 2.7 nF RDRP 576
RCP =
(2 fC )2 LE CE RFB VRAMP (2 140 *103 )2 (100 *10-9 / 6) (22 *10-6 62) 162 * 0.75 = = 1.65k VO 1.3 - 20 *10-3
10 LE CE RCP = 10 (100 *10-9 / 6) ( 22 *10-6 * 62) 1.65 103 = 27nF
CCP =
Choose CCP1=47pF to reduce high frequency noise. CURRENT SHARE LOOP COMPENSATION The crossover frequency of the current share loop fCI should be at least one decade lower than that of the voltage loop fC. Choose the crossover frequency of current share loop fCI=3.5kHz, and calculate CSCOMP,
FMI = RPWMRMP * CPWMRMP * f SW *V PWMRMP 18.2 *103 *100 *10-12 * 800 *103 * 0.75 = = 0.011 (VI - VPWMRMP - VDAC ) * (VI - VDAC ) (12 - 0.75 - 1.3) * (12 - 1.3) 0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2 * fCI * CE * (VO I O )] * FMI VO 2 fCI *1.05 *106
CSCOMP =
=
0.65 *18.2 *10 3 *12 *105 * 34 * (0.5 *10 -3 6) * [1 + 2 * 3500 * 22 *10 -6 * 62 * (1.33 - 105 * 9.1*10 -4 ) 105] * 0.011 (1.33 - 105 * 9.1*10 - 4 ) 2 3500 *1.05 *10 6
= 20.6nF
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LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. * * * * * * Dedicate at least one middle layer for a ground plane LGND. Connect the ground tab under the control IC to LGND plane through a via. Place the following critical components on the same layer as control IC and position them as close as possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, CVCC, and CSS/DEL. Avoid using any via for the connection. Place the compensation components on the same layer as control IC and position them as close as possible to EAOUT, FB and VDRP pins. Avoid using any via for the connection. Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes. Control bus signals, VDAC, RMPOUT, IIN, VBIAS, and especially EAOUT, should not cross over the fast transition nodes.
LGND PLANE
CCP1 RDRP CDRP RFB1 CCP RCP RFB
RDRP1
ROCSET
EAOUT
VBIAS
RVCC
CVCC
VCC LGND RMPOUT
FB
To VIN
BBFB
OCSET
VDRP
VDAC ROSC
CSS/DEL
SS/DEL PWRGD VOSNS-
To LGND
CVDAC
ROSC
RVDAC
IIN
VID5
VID1
VID2
VID3
VID0
VID4
ENABLE
To SYSTEM
To Voltage Remote Sense
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VOSNS+
VOSNS-
CFB
IR3081A
PCB Metal and Component Placement * Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. * Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. * Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be 0.17mm for 2 oz. Copper ( 0.1mm for 1 oz. Copper and 0.23mm for 3 oz. Copper) * A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC.
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Solder Resist * The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. * The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist is completely removed from between the lead lands forming a single opening for each "group" of lead lands. * At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. * The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. * Ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. * The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via.
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Stencil Design * The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. * The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. * The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. * The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
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PERFORMANCE CHARACTERISTICS
Figure 13 - Oscillator Frequency versus ROSC
1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 ROSC (K Ohms)
Oscillator Frequency (kHz)
Figure 14 - IFB, BBFB, & OCSET Bias Currents vs ROSC
125 115 105 95 85 75 uA 65 55 45 35 25 15 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 ROSC (K Ohm)
Figure 15 - VDAC Source & Sink Currents vc ROSC (includes OCSET Bias Current)
325 300 275 250 225 200 uA 175 150 125 100 75 50 25 0 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 ROSC (K ohm)
ISINK ISOURCE
Figure 16 - Bias Current Accuracy versus ROsC (includes temperature and input voltage variation)
14% 12% +/-3 Sigma Variation (%) 10% 8% 6% 4% 2% 0%
1 0 1 5 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 1 00
FB, BBFB, OCSET Bias Current VDAC Sink Current VDAC Source Current
ROSC (K Ohm)
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IR3081A
PACKAGE INFORMATION
28L MLPQ (5 x 5 mm Body) - JA = 30oC/W, JC = 3oC/W
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com
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1/31/05

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